1. Field of the Invention
The present invention relates to an interface circuit, and more particularly to an interface circuit that sends data, which has been applied to a block not in sync with a system clock, toward another block in sync with the system clock.
2. Description of Related Art
In the case of configuring a system using plural functional circuits, there is a possibility that the functional circuits receive/transmit data not synchronized with a system clock. In such a case, it is necessary to provide an interface circuit including a synchronizing circuit for synchronizing the data asynchronous with the system clock with the system clock. As an example of the interface circuit, there is an interface circuit provided between a mobile DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) and a memory controller. FIG. 6 is a block diagram showing a data processing system 100 including an interface circuit of the Related Art 1.
As shown in FIG. 6, the data processing system 100 of the Related Art 1 includes a CPU 110, a clock generator 111, a memory controller 112, an interface circuit 113, and a DDR-SDRAM 114.
Each block of the data processing system 100 operates in response to a reference clock (for example, sysCLK) generated with the clock generator 111. The CPU 110 processes data based on a command of an application stored in a storage device or the like (not shown). Further, the CPU 110 transmits/receives data to/from the memory controller 112 and to/from the DDR-SDRAM 114 through the interface circuit 113 as needed.
Upon the data transmission/reception, the DDR-SDRAM 114 transmits data DQ in sync with a strobe signal DQS asynchronous with a system clock sysCLK. However, the memory controller 112 cannot accurately receive the data unless the data is synchronized with the system clock sysCLK. To that end, the interface circuit 113 accurately receives the data DQ from the DDR-SDRAM 114, converts the data DQ into read data that can be accurately received by the memory controller 112 to change a synchronous timing, and transmits the read data to the memory controller 112. That is, the interface circuit 113 arbitrates between blocks that operate at different synchronous timings.
The interface circuit 113 adjusts a signal synchronous timing with a read data synchronizing unit 140 incorporated in the interface circuit 113. The synchronous timing is adjusted as follows. The read data synchronizing unit 140 includes a DLL (Delay Locked Loop) circuit 142, a sampling circuit 143 (includes flip-flop FF10 and FF11), a synchronizing circuit 144 (includes flip-flop FF12 and FF13), and a read data synchronizing unit 145.
First, when receiving the strobe signal DQS and the data DQ from the DDR-SDRAM 114, the DLL 142 gives a predetermined delay time (for example, a phase lag of 90°) to the strobe signal to generate a delayed strobe signal D_DQS. Next, the sampling circuit 143 samples the data DQ based on the delayed strobe signal D_DQS. At this time, since the data DQ is sampled based on the delayed strobe signal D_DQS, it is possible to sample the data in a period in which the data is stabilized, not changed.
Next, the synchronizing circuit 144 latches the data sampled with the sampling circuit 143 in response to the system clock sysCLK. Hence, the data DQ becomes a signal synchronous with the system clock sysCLK. A read data output unit adjusts a bit length of the data DQ synchronized with the system clock sysCLK by the synchronizing circuit 144 to output the adjusted data as read data to the memory controller 112.
However, the interface circuit 113 and the DDR-SDRAM 114 are generally mounted onto different semiconductor substrates, that is, embedded in different chips. Thus, the interface circuit 113 and the DDR-SDRAM 114 are connected through a line with some length, so a delay occurs in a signal transmitted/received on the line due to a resistance or capacitance of the line.
The interface circuit 113 of the Related Art 1 has a problem in that arbitration cannot be accurately executed depending on a delay of the strobe signal with respect to the system clock sysCLK. The operation of this case is explained below. FIG. 7 is a timing chart in the case where the strobe signal DQS is given a large delay relative to the system clock sysCLK, and the case where the strobe signal DQS is given a small delay relative to the system clock sysCLK.
As shown in FIG. 7, in the interface circuit of the Related Art 1, if the synchronizing circuit 144 is set to latch data [a] Lower, [a] Upper, [b] Lower, and [b] Upper inputted in synchronization with the strobe signal DQS and sampled with the sampling circuit 143 on the rising edge of the system clock sysCLK on the assumption that the strobe signal DQS has a large delay relative to the system clock sysCLK, when the input strobe signal DQS has a small delay relative to the system clock sysCLK, the synchronizing circuit 144 cannot latch lower-bit data [b] Lower of the data DQ (timing Tb).
Further, if the synchronizing circuit 144 is set to latch data [a] Lower, [a] Upper, [b] Lower, and [b] Upper inputted in synchronization with the strobe signal DQS and sampled with the sampling circuit 143 on the falling edge of the system clock sysCLK on the assumption that the strobe signal DQS has a small delay relative to the system clock sysCLK, when the input strobe signal DQS has a large delay relative to the system clock sysCLK, the synchronizing circuit 144 cannot latch upper-bit data [a] Upper of the data DQ (timing Ta).
That is, the interface circuit 113 of the Related Art 1 cannot execute accurate arbitration depending on a delay of the strobe signal DQS with respect to the system clock sysCLK.
Japanese Unexamined Patent Application Publication No. 2005-78547 discloses a technique for solving the above problem (Related Art 2). FIG. 8 shows an interface circuit 213 of the Related Art 2.
A sampling circuit 242 of a read data generating unit 240 of the interface circuit 213 of the Related Art 2 latches data DQ using a strobe signal DQS delayed by a DLL 243 similarly to the Related Art 1. The data DQ latched by the sampling circuit 242 is synchronized with the system clock sysCLK by a timing adjusting circuit 246 and then output to the memory controller 212.
A timing adjusting circuit 246 of the interface circuit 213 of the Related Art 2 has two data synchronizing paths (delay max and delay min) corresponding to different delay times. An appropriate one of the two paths is selected depending on a delay of the strobe signal DQS relative to the system clock sysCLK to thereby output the data DQ of the selected synchronizing path.
A delay determining circuit 244 determines a delay of the strobe signal DQS relative to the system clock sysCLK, and a hold circuit 245 holds the determination result of the delay determining circuit 244. The timing adjusting circuit 246 selects based on a bit selection signal and outputs the data DQ on the delay-max path for a large delay and selects based on the bit selection signal and outputs the data DQ on the delay-min path for a small delay based on the information stored in the hold circuit 245.
The timing adjusting circuit 246 of the interface circuit 213 of the Related Art 2 has tow data synchronizing paths corresponding to different delay times, and the delay determining circuit 244 determines the delay of the strobe signal DQS relative to the system clock sysCLK. Based on the result of determining the delay, the timing adjusting circuit 246 selects the synchronizing path corresponding to the determined delay to output the data DQ on the selected path. As a result, the interface circuit 213 of the Related Art 2 can accurately synchronize the data DQ with the system clock sysCLK regardless of whether the strobe signal DQS has a large delay or a small delay with respect to the system clock sysCLK.
However, the delay of the strobe signal DQS and the data DQ is almost determined depending on, for example, a board design, a power source, or other such conditions in many cases. That is, the interface circuit 213 of the Related Art 2 has a problem that the two synchronizing paths are being active all the time, so a circuit that is not so used consumes considerable power, and power consumption increases more than necessary.
Further, the interface circuit 213 of the Related Art 2 dynamically switches the synchronizing paths, so it is difficult to detect which synchronizing path is tested upon the circuit functional test for delivery inspection. That is, it is difficult to test the interface circuit 213 with reliability.